(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making field effect transistors (FETs) having titanium silicide source/drain areas and tungsten silicide FET gate electrodes that reduce the source/drain and gate electrode resistance and improve device performance.
(2) Description of the Prior Art
Field effect transistors (FETs) are used in the semiconductor industry for Ultra Large Scale Integration (ULSI) circuits. The FETs are formed using patterned conductively doped polysilicon layers for the gate electrodes and diffused self-aligned doped areas in the substrate adjacent to the gate electrodes for the source/drain areas. The polysilicon layers and the source/drain areas, even though conductively doped, have more electrical resistance than metal or metal silicide layers. This higher resistance is generally undesirable because it increases the RC (resistance.times.capacitance) time delay of the circuit and reduces circuit performance (speed). Therefore, metal silicides are commonly used on the gate electrodes and on the source/drain areas to improve the performance.
One conventional method of forming the FETs with silicide gate electrodes and source/drain areas is to form the gate electrodes by patterning a multilayer of doped polysilicon, a metal silicide, and a cap oxide layer over the gate oxide on the device areas. The gate electrodes are then used as a diffusion or implant barrier mask to form self-aligned lightly doped source/drain areas in the substrate adjacent to the sides of the gate electrodes. Sidewall insulating spacers are formed on the gate electrode sidewalls and a second implant, aligned to the sidewall spacers, is used to form the source/drain contact areas. A metal is deposited and annealed (sintered) to form the silicide source/drain contact areas with low resistance. However, this requires additional etching steps to form the gate electrodes in the multilayer of oxide, silicide, and polysilicon, which also requires reasonably vertical sidewalls for forming the sidewall spacers.
Another method which saves processing steps is the self-aligned silicide (salicide) process in which both the silicide gate electrodes and source/drain areas are made at the same time. In this method the gate electrodes are formed from a single doped polysilicon layer, and after forming insulating sidewall spacers a single metal, such as titanium (Ti), is deposited and annealed to concurrently form the silicide source/drain areas and silicide gate electrodes. The unreacted Ti on the oxide sidewall spacers and on other oxide surfaces is removed to electrically isolate the silicide source/drains areas from the silicide gate electrodes. However, during annealing the silicon can diffuse in the metal on the sidewall spacers that is not easily removed. This results in unwanted electrical shorts between source/drain and gate electrodes.
Numerous methods have been described for making FETs with silicide gate electrodes and source/drains. For example, in U.S. Pat. No. 5,468,662, Havemann teaches a method for making thin film transistors (TFTs) and FETs with silicide source/drains and gate electrodes. Havemann uses the salicide process and therefore would be prone to source/drain-to-gate-electrode shorts. Another approach for making silicided FETs is described by Sitaram et al. in U.S. Pat. No. 5,352,631. Sitaram first forms a doped polysilicon gate electrode with a cap oxide layer and insulating sidewall spacers. A first metal is deposited and annealed to form the silicide source/drains. The cap oxide on the gate electrode is selectively removed, and a second metal is deposited and annealed to form the silicide gate electrodes. The method is intended to provide different silicides for the source/drain and gate electrodes, each having the best processing and electrical characteristics, but does not treat the shorting problem between source/drain and gate electrode. T. E. Tang et al., in U.S. Pat. No. 4,690,730, utilizes a cap oxide layer on top of a single titanium layer prior to annealing to avoid oxygen contamination and suppresses silicon outdiffusion through portions of the metal layer (titanium) during annealing to form the silicide source/drain areas and gate electrodes. Another invention, Hsu, U.S. Pat. No. 5,491,099 uses the conventional salicide process to form TiSi.sub.2 source/drain areas and gate electrodes. A selective etch is used to remove the sidewall spacers and trenches are etched in the silicon substrate in the sidewall spacer area. An angled ion implant is used to form lightly doped drains (LDDs). The trenches are then filled with an oxide to isolate the silicide source/drain areas from the silicide gate electrodes. However, it is necessary to control accurately the trench etch depth, and to avoid plasma etch damage.
However, there is still a need in the semi-conductor industry to make FETs with different metal silicides on the source/drains and gate electrodes while avoiding the need to pattern a multilayer of cap oxide/polysilicon to form the gate electrodes. And there is still a need to provide an FET process that avoids the electrical shorting problem associated with the salicide process.